EE
210 - COURSE SYLLABUS SPRING 2012
Instructor : K. Dudeck
Office : L-104
Hours : Hours
are posted, additional hours by appointment.
Text:
Eriwn, Basic Engineering Circuit Analysis, 10th
Edition, Wiley Publishing, 2011.
EE 210:
Circuits and Devices (4:3:3):
Introduction to electrical circuit analysis, linear networks,
electronic
devices, amplifiers, and time-domain transient and steady-state responses.
Prerequisites: Phys 212,
Prerequisites or concurrent: MATH250.
Policies:
1. Students are expected to read the listed
text sections prior to each lecture period.
(See outline)
2. Students are expected to complete the
assigned homework problems after each lecture
period. Selected homework problems from each set
will be assigned to be completed in
class and turned
in to be graded. (See outline)
3. At the end of each chapter students should
be prepared to discuss their solutions in
class.
4.
Regular class attendance is expected.
5. Five take home quizzes will be given during
duration of the course, students may elect
to work together
on these solutions, however excessive collaboration may affect
individual
performance on examinations.
6.
Academic integrity in expected. Cheating
will result in an issued zero for the said exam
or quiz. See attached PSU policy.
7. Grading:
Grading is strictly on a point system.
QUIZZES: 100 pts ( 5 at 20 pts each )
HOMEWORK 50 pts
LAB WORK : 50 pts
EXAM I : 100 pts
EXAM II : 100 pts
FINAL EXAM
: 100 pts
________
TOTAL : 500 pts
(A=450; B+=435; B=400;
C+=385; C=350; D=300)
Academic
Integrity at
Academic integrity mandates the
pursuit of teaching, learning, research, and
creative
activity in an open, honest, and responsible manner. An academic
community
that values integrity promotes the highest levels of personal honesty,
respect
for the rights, property, and dignity of others, and fosters an
environment
in which students and scholars can enjoy the fruits of their efforts.
Academic integrity includes
a commitment neither to engage in acts of
falsification,
misrepresentation, or deception, nor to tolerate such acts by other
members
of the community.
Academic integrity is a
fundamental value at
of
all our endeavors and must guide our actions every day as students and as
members
of the faculty, administration, and staff. Because we expect new and
continuing
members of the University community to meet the high standards that
are
the foundation of a
reinforced
frequently.
The primary responsibility
for supporting and promoting academic integrity lies
with
the faculty and administration, but students must be active participants. A
climate
of integrity is created and sustained through ongoing conversations
about
honesty, trust, fairness, respect, and responsibility and the embodiment of
these
values in the life of the University. Students and faculty should contribute
actively
to fostering a climate of academic integrity in all their scholarly
activities,
through discussions in first-year seminars and in other courses, and
through
involvement in college Academic Integrity Committees. The University
community should be
continually mindful of the need to preserve academic
integrity
even as technology changes methods of information access and use.
Colleges will provide all
faculty members and teaching assistants information
about
appropriate ways to promote academic integrity and handle dishonesty
cases.
Faculty members and graduate assistants must make clear their
expectations
about academic integrity in every course they teach.
As members of the Council of
Academic Deans, we strongly support efforts to
enhance
academic integrity at
collective
leadership to strengthen further the University's commitment to the
highest
standards of academic integrity.
August 29, 2000
EE 210 Tentative Outline and
Homework Assignments - K. Dudeck Text : Erwin 10th Edition 2011
|
Period |
Topic
|
LAB/Activity |
Text
Reading |
Problems
|
|
1 |
Fundamental Units |
<OPEN> |
1.1 |
1.4,7,9 -SET #1 |
|
2 |
Power |
|
1.2 |
1.16,20,45 |
|
3 |
Circuit Elements |
|
1.3 |
1.42,
2.3 |
|
4 |
Kirchoff's Laws |
LAB#1 |
2.1,2 |
2.18,19,29 |
|
5 |
Basic Circuits |
|
2.3,4 |
2.39,44,49 |
|
6 |
Homework |
|
|
|
|
7 |
Series & Parallel |
LAB #1 Cont. |
2.5,7 |
2.56,59,62,108–SET #2 |
|
8 |
V & I Dividers - Quiz
1 |
HW Set #1 |
2.6,8 |
2.51,53,70,71,120 |
|
9 |
Nodal Analysis |
|
3.1 |
3.3,5,9,13 |
|
10 |
(Continued) |
Multi-Sim |
|
3.24,25,40,50 |
|
11 |
Mesh Analysis |
|
3.2 |
3.55,56,58 -SET
#3 |
|
12 |
(Continued) |
|
3.3 |
3.68,81,86 |
|
13 |
Superposition |
Homework |
5.1,2 |
5.7,10 |
|
14 |
Equivalent Sources |
HW Set #2 |
|
5.85,89 |
|
15 |
Max Power |
|
5.4 |
5.106,108,109 |
|
16 |
Review |
EXAM 1 |
|
|
|
17 |
Thevenin &
Norton Theorems |
|
5.3 |
5.53,58,59,61 –SET
#4 |
|
18 |
(Continued) -Quiz
#2 |
|
|
5.60,63,67 |
|
19 |
Operational Amplifiers |
Lab #3 |
4.1,2, |
4.8,9,14,22 |
|
20 |
Op Amp Circuits |
HW Set #3 |
4.3,4,5 |
4.34,40,51 |
|
21 |
Homework |
|
|
|
|
22 |
Capacitance |
Lab #5 |
6.1 |
6.11,13,19 |
|
23 |
Inductance |
|
6.2 |
6.25,28,35 –SET
#5 |
|
24 |
L & C Combinations –Quiz #3 |
|
6.3,4 |
6.44,50,67,69 |
|
25 |
Source Free RL |
Lab #5 Cont |
7.1 |
7.11,19 |
|
26 |
Source Free RC |
HW Set #4 |
7.2 |
7.17,20 |
|
27 |
Homework |
|
|
|
|
28 |
Forced Response |
<OPEN> |
|
7. 32,33,63 |
|
29 |
Complete Response |
|
|
7. 34,39,44,72, |
|
30 |
Source Free Parallel RLC |
|
7.3 |
7. 89,92,95 –SET
#6 |
|
31 |
Source Free Series RLC –Quiz #4 |
Mult-Sim |
|
7. 90,100,103 |
|
32 |
Complex Arithmetic |
HW Set #5 |
Appendix |
Handout |
|
33 |
Homework |
|
|
|
|
34 |
Review |
EXAM II |
|
|
|
35 |
Sinusoidal Analysis |
|
8.1 |
8. 1,2,4 |
|
36 |
Sinusoidal Forced Response |
|
8.2 |
8. 5 |
|
37 |
Phasors |
LAB TBA |
8.3 |
8. 24 |
|
38 |
Phasor Relations |
|
8.4 |
8.
31,40 |
|
39 |
Impedance/Admittance |
|
8.5,6 |
8. 7,8,15,16 –SET
#7 |
|
40 |
AC Circuit Analysis –Nodal |
Homework |
8.7 |
8. 60,67 |
|
41 |
AC Circuit Analysis –Mesh |
HW Set #6 |
8.8 |
8.73,74 |
|
42 |
Cont – Frequency Response -Quiz
#5 |
|
|
8.88,105,126 |
|
43 |
Instantaneous and Average Power |
Homework |
9.1,2 |
9.2,3 |
|
44 |
Complex Power |
HW Set #7 |
9.6 |
9. 74,75 |
|
45 |
Review |
|
|
FINAL EXAM |